Mathmatic for Stochastic Gradient Descent in Neural networks
All contents is arranged from CS224N contents. Please see the details to the CS224N!
1. Update equation
\[\theta^{new} = \theta^{old}-\alpha\nabla_{\theta}J(\theta),\ \alpha=step\ size\ or\ learning\ rate\]
For each parameter,
\[\theta^{new} = \theta^{old}-\alpha\dfrac{\partial J(\theta)}{\partial\theta_j^{old}}\]
2. Backpropagation algorit...
The Concept of Neural Network and Technique
All contents is arranged from CS224N contents. Please see the details to the CS224N!
1. Neuron
A neuron is a generic computational unit that takes n inputs and produces a single output. What differentiates the outputs of different neurons is their parameters (also referred to as their weights). One of the most popular choices for neurons is the...
Dependency Parsing
All contents is arranged from CS224N contents. Please see the details to the CS224N!
Intro
Why do we need sentence structure?
Humans communicate complex ideas by composing words together into bigger units to convey complex meanings
Listeners need to work out what modifies [attaches to] what
A model needs to understand sentence structur...
CS224N W1. Basic concept and Framework in Nature Lanugage Process
All contents is arranged from CS224N contents. Please see the details to the CS224N!
1. One Hot Vector
Vector
\[\mathbb{R}^{|V| \times 1}\]
Example
\[w^{aardvar} = \begin{bmatrix}
1\\
0\\
0\\
\vdots\\
0
\end{bmatrix},
...
Olive Pro and Olive Max, Earbuds for hearing aid
In Olive Union, who designed, manufactured, and serviced the application for a hearing aid, I contributed to Olive Pro and Olive Max as a digital signal processing engineer in embedded systems.
The product, Olive Pro
In the hearing aid open-source platform, the clarity challenge is continuing to research for enhancing s...
Delay Locked Loop for PHY interface between DRAM and CPU
When designing the interface circuit between Memory and CPU, this circuit needs another block related to a different clock. Since not only two components but also every hardware had its clock rate, this independent circuit shoud need a synchronization when writing the data. For this reason, I started to design this circuit named Delay Locked Loo...
PHY interface between DRAM and CPU
This project started from the need to design the interface circuit between the CPU and Memory. Since not only two components but also every hardware had its clock rate, the independent circuit for synchronization is necessary. For this reason, the independent circuit for receiving and transceiving the amount of data between CPU and Memory is ess...
47 post articles, 6 pages.